To enable 3D IC realization, EDA tools have to support 3D capabilities, especially when dealing with physical aspects of the design flow. In 2D designs, a physical net corresponds to each logical net. However, this 1-to-1 correspondence cannot be realized in 3D ICs. During the design partitioning phase, different logic modules (IPs) can be assigned to different tiers of the 3D stack, by considering optimization criteria, such as connection density, die utilization technology node for a given die etc. In such cases, a single physical net is not enough to connect the two IPs. The connection has to pass through multiple dies and connect through instantiations of through-silicon-via (TSV) and bump pins (BP). Therefore, a more complex physical connection is needed to implement logical connections in 3D ICs. Moreover, each die will typically be represented by a partitioned netlist before detailed implementation. It is very important to maintain the relationship between the original logical net in a 3D designs and the various components of the net in the individual dies.